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[Other resource] xuliejiance

Description: 《序列检测器》绝对好用的EDA实验程序,已经通过测试！VHDL语言编写-"Sequence Detector" absolutely good for EDA experimental procedure, he has passed the test! VHDL language
Platform: | Size: 1205 | Author: 潘晓峰 | Hits:

[VHDL-FPGA-Verilog] xljc

Description: 文件列表(日期：2006090517~2009021104)
Platform: | Size: 12288 | Author: 孙彬 | Hits:

[Software Engineering] xuliejiance

Description: 《序列检测器》绝对好用的EDA实验程序,已经通过测试！VHDL语言编写-"Sequence Detector" absolutely good for EDA experimental procedure, he has passed the test! VHDL language
Platform: | Size: 1024 | Author: 潘晓峰 | Hits:

[Embeded-SCM Develop] expt81_schk

Description: 基于fpga和sopc的用VHDL语言编写的EDA序列检测器-FPGA and SOPC based on the use of VHDL language EDA sequence detector
Platform: | Size: 10240 | Author: 多幅撒 | Hits:

[VHDL-FPGA-Verilog] Sequencedetector

Description: 用VHDL语言实现的序列检测器 （以1010111为例）-Sequence detector (for example 1010111)
Platform: | Size: 1024 | Author: 赵珑 | Hits:

[VHDL-FPGA-Verilog] VHDL_design_of_sequence_detector

Description: VHDL中序列检测器的设计的实验报告，包括源代码-VHDL in the design of sequence detector test reports, including the source code
Platform: | Size: 5120 | Author: CXJ | Hits:

[VHDL-FPGA-Verilog] sequence_detector

Description: 用VHDL语言实现一个序列检测器，检测到规定的序列时输出一高电平-VHDL language used to implement a sequence detector, to detect the sequence provided a high level when the output of
Platform: | Size: 54272 | Author: qiang200021 | Hits:

[VHDL-FPGA-Verilog] ram

Description: vhdl program for random access memory and sequence detector
Platform: | Size: 1024 | Author: swap | Hits:

[VHDL-FPGA-Verilog] Seqcheck

Description: 用VHDL编写的序列检测器，是完整工程。-Written by VHDL sequence detector is a complete project.
Platform: | Size: 91136 | Author: | Hits:

[VHDL-FPGA-Verilog] EDA

Description: EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
Platform: | Size: 914432 | Author: 邓泽林 | Hits:

[VHDL-FPGA-Verilog] Program

Description: 用VHDL状态机设计一个8位序列信号检测器。-Design a state machine in VHDL 8-bit serial signal detector.
Platform: | Size: 1024 | Author: 釉雪Dreamer | Hits:

[VHDL-FPGA-Verilog] VHDL_design

Description: 以VHDL设计一有限状态机构成的序列检测器。序列检测器是用来检测一组或多组序列信号的电路，要求当检测器连续收到一组串行码（如1110010）后，输出为1，否则输出为0。-With VHDL Design into a finite state machine sequence detector. Sequence detector is used to detect the signal sequence of one or more groups of circuits, require that when the detector receives a consecutive serial number (eg 1110010), the output is 1, otherwise the output is 0.
Platform: | Size: 47104 | Author: 陈倩 | Hits:

[VHDL-FPGA-Verilog] VHDL-to-design-detector

Description: 用VHDL语言设计一个序列“111010”的检测器和该序列的发生器-VHDL language " 111010" to design a sequence detector and the sequence generator
Platform: | Size: 1024 | Author: 赵玉著 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.
Platform: | Size: 587776 | Author: yinyu | Hits:

[File Format] VHDL-sequence-detector

Description: VHDL 序列检测 对特定的序列进行检测-VHDL sequence detector
Platform: | Size: 436224 | Author: miracle | Hits:

[VHDL-FPGA-Verilog] VHDL-Code-and-TestBench-Code

Description: 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
Platform: | Size: 100352 | Author: jimmy020 | Hits:

[VHDL-FPGA-Verilog] MVA15_Japan_Harris_FPGA_Vivado_source

Description: Harris 角点检测 FPGA实现 Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector" Code:in VHDL and Verliog running on Zedboard(Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector", The 14th IAPR Conference on Machine Vision Applications (MVA 2015), MIRAIKAN: National Museum of Emerging Science and Innovation in Tokyo, Japan, 18-22 May 2015 video1 video2 Code:in VHDL and Verliog running on Zedboard)
Platform: | Size: 19456 | Author: sudohello | Hits:

[Other] wyz_CPLDback

Description: 印刷机上使用的错帖检测仪代码，配合dsp5146完成印刷机错帖检测功能(The wrong post detector code used in the printer and the dsp5146 to complete the wrong post detection function of the printer)
Platform: | Size: 793600 | Author: 吹吹风1 | Hits:

[VHDL-FPGA-Verilog] 1

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..)
Platform: | Size: 453632 | Author: zidting | Hits:

[VHDL-FPGA-Verilog] 2

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on.)
Platform: | Size: 454656 | Author: zidting | Hits:
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